ベル研出張報告 木下　基 稲田　智志

エタロンフィルター用半導体レーザーの作成 出張目的 ２セクション分割型半導体レーザーの作成 エタロンフィルター用半導体レーザーの作成 これらについて… 設計のためのノウハウを得る 結晶成長＆プロセスを行う 共同研究者との親善 語学力向上 観光

Map Murray Hill Crawford Hill

Crawford Hill 正面玄関 裏山から ホーンリフレクタアンテナ ！？

埋め込み型半導体レーザーの作成

p+-InP p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) 1.3μmＬＤ 20nm Grow successive n-InP, n-InGaAsP, p-InP on substrate by MOCVD. p+-InP p+-InGaAs 20nm 酸化防止のため 50nm 金属とのcontactのため p+-InP u-InP 800nm Q1.1 25nm InGaAsP n-InP Q1.3 150nm n-InP(sub) Q1.1 25nm

p+-InP p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Remove p+-InGaAs, p+-InP layers with HCl. p+-InP p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

SiO2(120nm) p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Deposit SiO2. SiO2(120nm) p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Spin-coat p-resist. Pre-bake　the resist. resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

mask resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Exposure mask resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

Develop resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Rinse & post bake resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Remove SiO2 with HF resist SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub) Remove resist. Form SiO2 stripes. SiO2 p+-InGaAs p+-InP u-InP InGaAsP n-InP n-InP(sub)

SiO2 p+-InGaAs u-InP p+-InP InGaAsP n-InP n-InP(sub) Deep Etching with HBr:HCl:HAc:H2O2 SiO2 p+-InGaAs u-InP p+-InP InGaAsP n-InP n-InP(sub)

SiO2 p+-InGaAs u-InP p+-InP InGaAsP n-InP n-InP(sub) 実際に再成長させる厚さ Deep Etching with HBr:HCl:HAc:H2O2 SiO2 p+-InGaAs u-InP p+-InP 実際に再成長させる厚さ InGaAsP n-InP n-InP(sub)

SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub) Regrow iron doped InP and n-InP layor on the wafer. SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub) Remove SiO2 with pure HF. SiO2 n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub) Remove InGaAs with H2SO4:H2O:H2O2. n-InP p+-InGaAs i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

ドープするZnの濃度を徐々に増やしていく。 regrow p++-InP layer ドープするZnの濃度を徐々に増やしていく。 n-InP p++-InP(2μm) i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP regrow p+-InGaAs and p+-InP layers p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP Paste p-resist. resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

mask resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Exposure mask resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP Develop resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP Deep etching to make trenches. resist p+-InP p+-InGaAs P-InP層のseparate n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP Remove resist. p+-InP p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

p+-InP SiO2（540nm） p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Deposit SiO2 p+-InP SiO2（540nm） p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Paste p-resist resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

mask resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP Exposure mask resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Develop resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Remove SiO2 with HF resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP Remove InP with HCl. resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

1st-metal(410nm) resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP Evaporate 1st-metal. 1st-metal(410nm) resist p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP Remove resist (lift-off). 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP Remove resist (lift-off). 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Put n-resist. resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

mask resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Exposure resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Develop resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Develop resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal(860nm) resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP Evaporate 2nd-metal. 2nd-metal(860nm) resist 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Remove resist. (Lift-Off) 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Lift-Off 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Thinning　to 200μm 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Thinning 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-InP(sub)

2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP Evaporate n-electrode 2nd-metal 1st-metal p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP metal(560nm) n-InP(sub)

p-electrode p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP 完成！ p-electrode p+-InP SiO2 p+-InGaAs n-InP p++-InP i-InP u-InP p+-InP InGaAsP n-InP n-InP n-electrode n-InP(sub)

ＬＤ 900μm 900μm 300μm 300μm

ＱＷＬＤ 900μm 900μm 300μm 300μm

Ｉ－Ｌ特性* Ｉ－Ｖ特性* 発振スペクトル* *いずれもQWLD、300mm

２セクション分割型半導体レーザー

２セクション分割型半導体レーザーの作成法 Selective Area Growth Butt Joint 再成長 基板上に蒸着されたSiO2膜によって生じる気相密度の偏りとマイグレーション によって、エネルギーギャップの異なる構造を同一基板上に生成する。 この部分に成長する量子井戸は、 他の領域のものよりも厚くなる （エネルギーは低くなる） 損失の小さいジョイントが可能 再成長の手間が省ける エネルギーの制御が困難 Q1.3 Q1.5 Butt Joint 1.5mm用層を成長後光リソグラフィによって選択的にエッチングを行い、 その後、 1.3mm用層を再成長させる。 SAGより確立された手法 ジョイントの損失が大きい Photo Resist & SiO2 p p p Q1.5 再成長 Q1.3 n n Substrate Substrate これらのプロセスには光リソグラフィ用のマスクが不可欠であり、今後それらの設計・作成から行わなければならない。

1.3mm帯DHと1.45mm帯QW半導体レーザーを作成した。 （共振器長300～1100mmのレーザーを計２５０個程入手） 達成状況 1.3mm帯DHと1.45mm帯QW半導体レーザーを作成した。 （共振器長300～1100mmのレーザーを計２５０個程入手） 透過測定による位相変調性の評価 HRコーディングを施し、エタロンフィルタとして使用 今後 ２セクション分割型半導体レーザーの作成方法についてディスカッションを行った。 プロセス用のマスクの設計と作成 →素子を作成する。 今後 高速広域変調デバイス(Coupled QW)に関するディスカッションを行った。 今後 理論の理解とデバイスの設計