Tohoku University Kyo Tsukada

Presentation on theme: "Tohoku University Kyo Tsukada"— Presentation transcript:

1 Tohoku University Kyo Tsukada
2007/4/4 NKS meeting Tohoku University Kyo Tsukada

2 Schematic view of DAQ system
K0daq2 : VME : Bit3 620 read TKO via SMP CAMAC : CC7700 receive interrupt read scaler K0daq1 : read AMT

3 Dead time of k0daq1 (from ppt at 2006/11/15)
AMT conversion time : nhit×5usec + 25usec AMT data structure : 2 header + data + 1 footer AMT read out : ~2usec/word Mean estimation #data at 1 event ~ 80 data #AMT at 1 event ~ 10 Conversion : 8×5+25 ~ 65 usec Read out : 100×2 ~ 200 usec Total : ~ 270 usec  ... In fact, The long tails exist. Please remove the noise on chamber…. Most easiest way to reduce the dead time is … One more DAQ PC …?

4 scheme Camac Interrupt register (k0daq2) Main trigger Common stop
No delay Exp. hall No delay Camac Interrupt register Unidaq starts polling and outputs the machine veto signal. If a AMT return the conversion end status, the data are read. When all AMTs become ready, unidaq cancels the machine veto signal. If we install new vertex chamber with larger channels, we need new system.

5 Multi event mode AMT can be used as multi event mode. The buffer is not large. The buffer is equally divided. If the buffer is fully used, the DMA transfer method may work well. I talked about this topic with Arai-san and Iri-san at 26 March.

6 アムスクから送られてきた仕様書 仕様書も日本語なので、日本語で。
要約すると、メモリの半分が埋まったところでAMTがreadyになる。その際に割り込みを出力するようにするか、ひたすらポーリングを行なうか、はまだ未定。 また、data conversion中にはbusy信号を現在未使用のNIM outputから出力してもらう。

7 Some problems Most serious problem is “correspondence among events and among modules”. Among modules: the data of common stop time included in event header may be available. Among events: If correspondence among modules become to be clear, the bit pattern method can be available by using one slot of AMT. B.G. exit constantly, but the discrepancy doesn’t expand.

8 AMT data Data structure Event header

9 AMT module